This invention relates generally to logic or memory circuits and more particularly, it relates to a static PLA or HOM circuit with self-generated precharge for generating a faster high-to-low transition on its output than those traditionally available.
As is generally known, a PLA (programmable logic array) or ROM (read-only memory) circuit is used to generate many minterms from a number of input select signals. In MOS technology, it is commonly implemented with an array of N-channel transistors connected in the form of a NOR logic gate. In FIG. 1(a), there is shown an example of a single minterm of a dynamic PLA circuit of the prior art. In FIG. 1(b), there is shown an example of a single minterm of a static PLA circuit of the prior art.
As can be seen in FIG. 1(a), the dynamic PLA circuit 10 includes a NOR logic gate formed of N-channel MOS transistors N1-N4 whose gates are connected to receive respective input select signals S1-54 and a precharge circuit portion consisting of a P-channel MOS transistor P1. The transistor P1 has its source connected to a supply potential VCC, drain connected to the output node 12 of the NOR gate, and gate connected to a precharge control input signal such as a clock signal CLOCK. While the dynamic PLA circuit performs adequately to produce fast transitions at the output node, it suffers from the disadvantage in that of requiring the use of the clock signal to switch on and off the transistor P1. Further, another disadvantage exists since there is required an extra lead connection to an external pin for receiving such a clock signal, thereby increasing manufacturing and software costs.
In order to overcome the disadvantages of the dynamic PLA circuit, there has been attempted heretofore the design of a static PLA circuit which does not require the utilization of a precharge control input signal. However, it does need an N-channel or P-channel MOS transistor, which is always turned on, to function as a pull-up device. One such static PLA circuit 14 is illustrated in the aforementioned FIG. 1(b). Since the P-channel transistor P1 is constantly turned on due to the fact that its gate is connected to a ground potential, this creates another problem when the output node A of the NOR gate is switched from the off-state to the on-state. As a result, there is a discharging of not only the charge previously stored at the output node A but also of the current from the P-channel transistor P1 which is always turned on. Therefore, this has the disadvantage of reducing the speed of the high-to-low transition at the output node A.
It would therefore be desirable to provide an improved static PLA circuit which has a fester high-to-low transition at its output than those of the prior art static PLA circuits. The static PLA circuit of the present invention includes a feedback path connected between the output of the logic gate and the gate of a pull-up device so as to increase substantially the speed of the high-to-low transition at the output node.